1. Field of the Invention
The present invention relates to a solid state image sensor, and, more particularly, to a solid state image sensor in which a charge generated in a photodiode can easily transfer to a vertical charge coupled device.
2. Discussion of the Related Art
In general, a solid state image sensor has photoelectric conversion cells (for example, photodiodes) and charge coupled devices for taking an image and outputting an electric signal corresponding to the image. The charge coupled device utilizes a potential difference in a substrate for transmitting a charge generated in the photoelectric conversion cells in a particular direction. The solid state image sensor includes a large number of photoelectric conversion cells, and vertical charge coupled devices (VCCDs) formed between the photoelectric conversion cells for transmission of the charges generated in the photoelectric conversion cells in a vertical direction. The solid state image sensor also includes a horizontal charge coupled device (HCCD) for transmission of the signal charges transmitted in the vertical direction by the VCCDs in a horizontal direction again, and a floating diffuser for sensing and amplifying the electric signal transmitted in the horizontal direction and outputting the signal changes to peripheral circuits.
The conventional solid state image sensor will be further explained with reference to the attached drawings. FIG. 1 illustrates a layout of the conventional solid state image sensor, FIG. 2a illustrates a section of the conventional solid state image sensor shown in FIG. 1 across line I-I', FIGS. 2b and 2c illustrate potential profiles of the conventional solid state image sensor shown in FIG. 2a, and FIG. 3 is a cross-section across line II-II' of FIG. 1. For ease of explanation, the photodiode of FIG. 1 will be referred to as having a top side, a left side, a right side, and a bottom side. The top-bottom direction will be referred to as vertical direction (corresponding to a direction of a column of photodiodes in a matrix), and the left-right direction will be referred to as horizontal direction (corresponding to a direction of a row of photodiodes). It will be clear to one skilled in the art that the designations of directions are arbitrary and illustrative onlv.
Referring to FIGS. 1 and 2a, the conventional solid state image sensor includes a photodiode 5 having a PD-N region 3 and a PD-P region 4 in a first p-type well region 2 formed in an n-type semiconductor substrate 1 for converting a photo signal into an electric signal. A vertical charge coupled device (VCCD) 8 is located to the right of the photodiode 5 for transmission of the charge from the photodiode 5 in a vertical direction. A channel stop layer 7 is formed around the photodiode 5 and excluding a portion of the photodiode 5 on the right side of the photodiode 5 which is used to transmit the charge outputted by the photodiode 5 to the VCCD 8. First and second polygates 9 and 10 are formed in part over the VCCD 8 and in part overlapping each other, as shown in FIG. 1. The VCCD 8 is formed in a second p-type well 6 formed in the first p-type well 2 excluding portions of the photodiode 5 and the channel stop layer 7. The portion through which the electric signal from the photodiode 5 is transmitted to the VCCD 8 is formed on the right side of the photodiode 5. A width of a side of the photodiode 5 facing the VCCD 8 (i.e. the dimension of the right side of the photodiode 5 in the vertical direction) is denoted as "A". The second polvgate 10 has a second polygate extension extending in a downward vertical direction between the photodiodes 5, located to the right of the photodiode 5 and partly overlapping the VCCD 8. The first polygate 9 has a first polyate extension extending in an upward vertical direction from the second polygate 9, partlv overlapping the second polvgate extension 10a, located to the right of the photodiode 5 and partlv overlapping the VCCD 8. A width of the photodiode 5 corresponding to the second polygate extension 10a (which is used to transmit the charge from the photodiode 5 to the VCCD 8) is denoted as "B". A width of a gap in the channel stop region 7 on the right side of the photodiode 5 through which the charge from the photodiode 5 can be transmitted (i.e. a region around the photodiode 5 without the channel stop layer 7) is denoted as "C".
The potential profiles of the conventional solid state image sensor will be explained with reference to FIGS. 2b and 2c.
FIG. 2b illustrates a potential profile in the photodiode 5 after the photodiode 5 has been generating charge for a certain time period. With a bias of between 0 and 9 v applied to the second polygate 10 (which is used as a transfer gate), the photodiode 5 outputs the charge to the HCCD (not shown) step by step according to clock pulses applied to the first polygate 9 (not shown in FIG. 2a) when a voltage level of the first polygate 9 is different from a voltage level of the second polygate 10. In this case, the first p-type well 2 between the n-type VCCD 8 and the photodiode 5 acts as a barrier that blocks the charge collected in the photodiode 5 from being transmitted to the VCCD 8.
FIG. 2c illustrates a potential profile in the photodiode 5 when charge generated in the photodiode 5 for the certain time period is being transferred to the VCCD 8. With a bias as high as 15 v applied to the second polygate 10 (which is used as a transfer gate), the potential in the first p-type well 2 which acted as the barrier between the VCCD 8 and the photodiode 5 is lowered, allowing a transfer of the charge in the photodiode 5 to the VCCD 8, so that the charge can then be read out. That is, referring to FIG. 1, the voltage of the polygate 10 is lowered to read out the charge generated in the photodiode 5 through a side corner portion of the photodiode 5 (i.e. top right corner), rather than a center portion of the photodiode 5.
FIG. 3 illustrates a cross-section of the conventional solid state image sensor across line
II-II' of FIG. 1, showing different layers above and below the VCCD 8.
Referring to FIG. 3, the conventional solid state image sensor includes first and second p-type wells 2 and 6 in an n-type semiconductor substrate 1, a VCCD 8 formed in the second p-type well 6, a first polygate 9 over the VCCD 8, and a second polygate 10 at a side of the first polygate 9 whose edge portion overlaps an edge portion of the first polygate 9.
FIG. 4 illustrates a potential contour when a high bias is applied to the second polygate 10, which is used as a transfer gate in the conventional solid state image sensor.
Referring to FIG. 4, the charge generated in the photodiode 5 is read out when the high bias of 15 v is applied to the transfer gate through the portion of the first p-type well 2 overlapping the photodiode 5, and the potential in the portion of the first p-type well 2 is lowered by the high bias applied to the second polygate 10. However, since the portion through which the charges are read out lies not at the center, but in the comer of the photodiode 5, some of the charges generated in the photodiode 5 are not read out completely, but remain in the photodiode 5 (denoted as portion "D") for a certain duration. This reduces efficiency of the solid state image sensor, resulting in a degraded picture quality.